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Computer Engineering Study Notes
Comprehensive Study Guide for CpE Students
In This Guide
About Computer Engineering
Computer Engineering (CpE) combines electrical engineering and computer science to develop computer hardware and software. Unlike other engineering fields, CpE does not have a PRC board exam in the Philippines. This study guide covers core topics for CpE students.
Core Topics
- • Digital Logic & Circuit Design
- • Computer Architecture
- • Microprocessors & Embedded Systems
- • Data Communications & Networks
- • Software Engineering
Career Paths
- • Hardware Engineer
- • Embedded Systems Developer
- • Network Engineer
- • Software Developer
- • Systems Architect
Part 1: Digital Logic Design
Number Systems
Conversions
Common Bases
- Binary (Base 2): 0, 1
- Octal (Base 8): 0-7
- Decimal (Base 10): 0-9
- Hexadecimal (Base 16): 0-9, A-F
Binary-Hex Quick Reference
0000 = 01000 = 80001 = 11001 = 90010 = 21010 = A0011 = 31011 = B0100 = 41100 = C0101 = 51101 = D0110 = 61110 = E0111 = 71111 = F
Binary Arithmetic
- 2's Complement: Invert all bits + 1 (for negative numbers)
- Sign-Magnitude: MSB is sign bit (0=+, 1=-)
- BCD: Each decimal digit = 4 bits (0-9 only)
- Gray Code: Only 1 bit changes between consecutive values
Logic Gates
AND
Y = A · B
Output 1 only if all inputs are 1
OR
Y = A + B
Output 1 if any input is 1
NOT
Y = A'
Inverts the input
NAND
Y = (A · B)'
Universal gate
NOR
Y = (A + B)'
Universal gate
XOR
Y = A ⊕ B
Output 1 if inputs differ
Boolean Algebra
Laws & Theorems
- Identity: A + 0 = A, A · 1 = A
- Null: A + 1 = 1, A · 0 = 0
- Idempotent: A + A = A, A · A = A
- Complement: A + A' = 1, A · A' = 0
- Commutative: A + B = B + A
- Associative: (A + B) + C = A + (B + C)
- Distributive: A(B + C) = AB + AC
- De Morgan's: (AB)' = A' + B', (A+B)' = A'B'
Sequential Circuits
Flip-Flops
- SR Flip-Flop: Set-Reset; S=R=1 invalid
- D Flip-Flop: Data; Q follows D on clock edge
- JK Flip-Flop: No invalid state; J=K=1 toggles
- T Flip-Flop: Toggle; toggles when T=1
Applications
- • Counters (synchronous/asynchronous)
- • Registers (shift, parallel)
- • Memory elements
- • State machines
Part 2: Computer Architecture
CPU Components
Control Unit (CU)
- • Fetches instructions from memory
- • Decodes instructions
- • Controls data flow
- • Generates timing signals
ALU
- • Arithmetic operations (+, -, ×, ÷)
- • Logical operations (AND, OR, NOT)
- • Comparison operations
- • Shift operations
CPU Registers
- Program Counter (PC): Address of next instruction
- Instruction Register (IR): Current instruction being executed
- Accumulator (ACC): Stores intermediate results
- Stack Pointer (SP): Top of stack address
- Status Register: Flags (Zero, Carry, Sign, Overflow)
Memory Hierarchy
Speed (Fast → Slow) / Cost (High → Low)
- Registers (inside CPU)
- Cache Memory (L1, L2, L3)
- Main Memory (RAM)
- Secondary Storage (SSD, HDD)
- Tertiary Storage (Tape, Optical)
Cache Concepts:
- • Hit Rate: % of accesses found in cache
- • Miss Penalty: Time to fetch from lower level
- • Mapping: Direct, Associative, Set-Associative
Instruction Cycle
Fetch-Decode-Execute
- Fetch: Get instruction from memory using PC
- Decode: Determine operation and operands
- Execute: Perform the operation
- Store: Write results to memory/register
Part 3: Microprocessors & Embedded Systems
8086/8088 Architecture
Registers
General Purpose
- AX (Accumulator)
- BX (Base)
- CX (Counter)
- DX (Data)
Segment Registers
- CS (Code Segment)
- DS (Data Segment)
- SS (Stack Segment)
- ES (Extra Segment)
Physical Address Calculation
Physical Address = Segment × 16 + Offset
Example: CS=1000h, IP=0100h → 10000h + 0100h = 10100h
Assembly Language Basics
Common Instructions
Data Transfer
- MOV dest, src
- PUSH reg
- POP reg
- XCHG dest, src
Arithmetic/Logic
- ADD dest, src
- SUB dest, src
- MUL src
- AND, OR, XOR, NOT
Microcontrollers
8051 Architecture
- RAM: 128 bytes internal
- ROM: 4KB internal (8751)
- I/O Ports: 4 × 8-bit (P0-P3)
- Timers: 2 × 16-bit
- Serial Port: Full duplex UART
- Interrupts: 5 sources, 2 priority levels
Part 4: Data Communications & Networks
OSI Model
7. ApplicationHTTP, FTP, SMTP, DNS
6. PresentationSSL/TLS, JPEG, ASCII
5. SessionNetBIOS, RPC
4. TransportTCP, UDP
3. NetworkIP, ICMP, Routers
2. Data LinkEthernet, MAC, Switches
1. PhysicalCables, Hubs, Signals
TCP/IP
TCP (Reliable)
- • Connection-oriented
- • Guaranteed delivery
- • Flow control
- • 3-way handshake (SYN, SYN-ACK, ACK)
UDP (Fast)
- • Connectionless
- • No guarantee
- • Lower overhead
- • Used for streaming, DNS, VoIP
IP Addressing
IPv4 Classes
| Class | Range | Default Mask | Use |
|---|---|---|---|
| A | 1-126 | 255.0.0.0 | Large networks |
| B | 128-191 | 255.255.0.0 | Medium networks |
| C | 192-223 | 255.255.255.0 | Small networks |
| D | 224-239 | N/A | Multicast |
| E | 240-255 | N/A | Reserved |
Private IP Ranges:
- • 10.0.0.0 - 10.255.255.255 (Class A)
- • 172.16.0.0 - 172.31.255.255 (Class B)
- • 192.168.0.0 - 192.168.255.255 (Class C)
Part 5: Software Engineering
Software Development Models
Waterfall
- 1. Requirements
- 2. Design
- 3. Implementation
- 4. Testing
- 5. Deployment
- 6. Maintenance
Agile/Scrum
- • Iterative development
- • Sprints (2-4 weeks)
- • Daily standups
- • User stories
- • Continuous feedback
Data Structures
Linear
- Array: Fixed size, O(1) access
- Linked List: Dynamic, O(n) access
- Stack: LIFO (Last In First Out)
- Queue: FIFO (First In First Out)
Non-Linear
- Tree: Hierarchical (Binary, BST, AVL)
- Graph: Nodes + Edges
- Hash Table: Key-value, O(1) average
- Heap: Complete binary tree
Algorithm Complexity
Big-O Notation
- O(1): Constant - Array access
- O(log n): Logarithmic - Binary search
- O(n): Linear - Linear search
- O(n log n): Linearithmic - Merge sort, Quick sort (avg)
- O(n²): Quadratic - Bubble sort, Selection sort
- O(2ⁿ): Exponential - Recursive Fibonacci
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