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Study Notes55 min read

Microprocessors & Embedded Systems

8086/8088, 8051 Microcontroller, ARM & Interfacing

1. 8086/8088 Architecture

Overview

8086 Specifications:

  • • 16-bit microprocessor
  • • 16-bit data bus
  • • 20-bit address bus (1 MB addressable)
  • • 40-pin DIP package
  • • 5 MHz to 10 MHz clock

8088 Differences:

  • • 8-bit external data bus
  • • Same internal 16-bit architecture
  • • Used in original IBM PC
  • • Slower memory transfers

Internal Architecture

The 8086 has two processing units that operate in parallel:

Bus Interface Unit (BIU)

  • • Fetches instructions from memory
  • • Manages segment registers (CS, DS, SS, ES)
  • • Contains instruction queue (6 bytes)
  • • Generates 20-bit physical address

Execution Unit (EU)

  • • Decodes and executes instructions
  • • Contains ALU
  • • Manages general purpose registers
  • • Generates control signals

Register Set

General Purpose Registers (16-bit, split into 8-bit H/L):

AX (AH|AL)

Accumulator

BX (BH|BL)

Base

CX (CH|CL)

Counter

DX (DH|DL)

Data

Segment Registers (16-bit):

CS

Code Segment

DS

Data Segment

SS

Stack Segment

ES

Extra Segment

Pointer & Index Registers:

SP

Stack Pointer

BP

Base Pointer

SI

Source Index

DI

Dest Index

Physical Address Calculation

Physical Address = Segment × 16 + Offset

or: Physical Address = Segment × 10h + Offset

Example:

CS = 1000h, IP = 0100h

Physical = 1000h × 10h + 0100h = 10000h + 0100h = 10100h

2. 8086 Assembly Language

Data Transfer Instructions

General:

  • MOV dest, src ; dest ← src
  • XCHG dest, src ; swap values
  • LEA reg, mem ; load effective address

Stack:

  • PUSH reg ; SP-=2, [SP]←reg
  • POP reg ; reg←[SP], SP+=2
  • PUSHF ; push flags
  • POPF ; pop flags

Arithmetic Instructions

Addition/Subtraction:

  • ADD dest, src
  • ADC dest, src ; with carry
  • SUB dest, src
  • SBB dest, src ; with borrow
  • INC reg ; reg++
  • DEC reg ; reg--

Multiplication/Division:

  • MUL src ; AX = AL × src (unsigned)
  • IMUL src ; signed multiply
  • DIV src ; AL=AX/src, AH=remainder
  • IDIV src ; signed divide
  • NEG reg ; 2's complement

Logical Instructions

Bitwise:

  • AND dest, src
  • OR dest, src
  • XOR dest, src
  • NOT reg
  • TEST dest, src ; AND without storing

Shift/Rotate:

  • SHL reg, count ; shift left
  • SHR reg, count ; shift right
  • SAR reg, count ; arithmetic shift
  • ROL reg, count ; rotate left
  • ROR reg, count ; rotate right

Control Flow Instructions

Jumps:

  • JMP label ; unconditional
  • JE/JZ label ; jump if equal/zero
  • JNE/JNZ label ; jump if not equal
  • JG/JNLE label ; jump if greater (signed)
  • JL/JNGE label ; jump if less (signed)
  • JA/JNBE label ; jump if above (unsigned)
  • JB/JNAE label ; jump if below (unsigned)

Procedures & Loops:

  • CALL label ; push IP, jump
  • RET ; pop IP, return
  • LOOP label ; CX--, jump if CX≠0
  • LOOPE label ; loop while equal
  • LOOPNE label ; loop while not equal
  • CMP dest, src ; compare (sets flags)

3. Interrupts

Types of Interrupts

Hardware Interrupts

  • NMI (Non-Maskable): Cannot be disabled
  • INTR (Maskable): Can be disabled via IF flag
  • Triggered by external devices
  • Priority: NMI > INTR

Software Interrupts

  • Triggered by INT instruction
  • INT 21h: DOS services
  • INT 10h: Video BIOS
  • INT 13h: Disk BIOS
  • INT 16h: Keyboard BIOS

Interrupt Vector Table (IVT)

  • • Located at address 0000:0000 to 0000:03FF
  • • 256 interrupt vectors (0-255)
  • • Each vector = 4 bytes (2 for IP, 2 for CS)
  • • Total size = 1 KB

Vector Address = Interrupt Number × 4

Example: INT 21h → 21h × 4 = 84h

Interrupt Processing

  1. Complete current instruction
  2. Push FLAGS onto stack
  3. Clear IF and TF flags
  4. Push CS onto stack
  5. Push IP onto stack
  6. Load new IP and CS from IVT
  7. Execute ISR (Interrupt Service Routine)
  8. IRET instruction restores IP, CS, FLAGS

4. 8051 Microcontroller

Architecture Overview

Features:

  • • 8-bit microcontroller
  • • 4 KB internal ROM (8751: EPROM)
  • • 128 bytes internal RAM
  • • 4 × 8-bit I/O ports (P0-P3)
  • • 2 × 16-bit timers (T0, T1)
  • • Full duplex serial port
  • • 5 interrupt sources
  • • 40-pin DIP package

Memory Map:

  • 00h-1Fh: Register banks (4 × 8)
  • 20h-2Fh: Bit addressable
  • 30h-7Fh: General purpose RAM
  • 80h-FFh: Special Function Registers

Special Function Registers (SFRs)

  • A (E0h): Accumulator
  • B (F0h): B register (MUL/DIV)
  • PSW (D0h): Program Status Word
  • SP (81h): Stack Pointer
  • DPTR: Data Pointer (DPL/DPH)
  • P0-P3: I/O Ports
  • TMOD: Timer Mode
  • TCON: Timer Control
  • SCON: Serial Control
  • IE: Interrupt Enable
  • IP: Interrupt Priority

PSW (Program Status Word)

| CY | AC | F0 | RS1 | RS0 | OV | - | P |
  • CY (PSW.7): Carry flag
  • AC (PSW.6): Auxiliary carry (BCD)
  • F0 (PSW.5): User flag
  • RS1:RS0: Register bank select (00=Bank0, 01=Bank1, 10=Bank2, 11=Bank3)
  • OV (PSW.2): Overflow flag
  • P (PSW.0): Parity (1 if odd number of 1s in A)

I/O Ports

Port 0 (P0):

  • • Address/Data bus (multiplexed)
  • • Open-drain (needs pull-up)
  • • 8 pins: P0.0 - P0.7

Port 1 (P1):

  • • General purpose I/O
  • • Internal pull-ups
  • • 8 pins: P1.0 - P1.7

Port 2 (P2):

  • • High-order address bus
  • • Internal pull-ups
  • • 8 pins: P2.0 - P2.7

Port 3 (P3):

  • • Alternate functions: RxD, TxD, INT0, INT1, T0, T1, WR, RD
  • • Internal pull-ups
  • • 8 pins: P3.0 - P3.7

Timer Modes (TMOD)

  • Mode 0: 13-bit timer (8048 compatible)
  • Mode 1: 16-bit timer (most common)
  • Mode 2: 8-bit auto-reload (baud rate generator)
  • Mode 3: Split timer (T0 only)

Timer Calculation (Mode 1):

Count = 65536 - (Delay × (Fosc/12))

For 11.0592 MHz crystal: Machine cycle = 1.085 μs

5. 8051 Instruction Set

Data Transfer

  • MOV A, Rn ; A ← Rn
  • MOV A, direct ; A ← memory
  • MOV A, @Ri ; A ← [Ri]
  • MOV A, #data ; A ← immediate
  • MOVC A, @A+DPTR ; code memory
  • MOVX A, @DPTR ; external RAM
  • PUSH direct ; push to stack
  • POP direct ; pop from stack

Arithmetic & Logic

  • ADD A, src ; A = A + src
  • ADDC A, src ; with carry
  • SUBB A, src ; A - src - C
  • MUL AB ; B:A = A × B
  • DIV AB ; A = A/B, B = A%B
  • ANL A, src ; AND
  • ORL A, src ; OR
  • XRL A, src ; XOR
  • CLR A ; A = 0
  • CPL A ; complement A

Branching

  • LJMP addr16 ; long jump
  • AJMP addr11 ; absolute jump
  • SJMP rel ; short jump (-128 to +127)
  • JMP @A+DPTR ; indirect jump
  • JZ rel ; jump if A = 0
  • JNZ rel ; jump if A ≠ 0
  • DJNZ Rn, rel ; dec and jump if ≠ 0
  • CJNE A, #data, rel ; compare and jump if not equal

Bit Instructions

  • SETB bit ; set bit to 1
  • CLR bit ; clear bit to 0
  • CPL bit ; complement bit
  • JB bit, rel ; jump if bit = 1
  • JNB bit, rel ; jump if bit = 0
  • JBC bit, rel ; jump if bit = 1, then clear

6. ARM Processors

ARM Architecture Features

Key Characteristics:

  • • 32-bit RISC processor
  • • Load/Store architecture
  • • 16 general purpose registers (R0-R15)
  • • Conditional execution on most instructions
  • • Thumb mode (16-bit instructions)
  • • Low power consumption

Special Registers:

  • R13 (SP): Stack Pointer
  • R14 (LR): Link Register
  • R15 (PC): Program Counter
  • CPSR: Current Program Status
  • SPSR: Saved Program Status

ARM vs Thumb Mode

ARM Mode

  • • 32-bit instructions
  • • Full feature set
  • • Higher performance
  • • More memory usage

Thumb Mode

  • • 16-bit instructions
  • • Subset of ARM features
  • • Better code density
  • • Lower power consumption

ARM Processor Families

Cortex-M (Microcontroller)

M0, M0+, M3, M4, M7 - Embedded, real-time applications

Cortex-R (Real-time)

R4, R5, R7, R8 - Safety-critical systems, automotive

Cortex-A (Application)

A5, A7, A9, A53, A72 - Smartphones, tablets, servers

7. Interfacing

Common Interface ICs

8255 (PPI)

  • • Programmable Peripheral Interface
  • • 3 × 8-bit ports (A, B, C)
  • • Mode 0: Simple I/O
  • • Mode 1: Strobed I/O
  • • Mode 2: Bidirectional (Port A only)

8259 (PIC)

  • • Programmable Interrupt Controller
  • • 8 interrupt inputs
  • • Cascadable (up to 64 interrupts)
  • • Priority modes: Fully nested, Rotating

8253/8254 (PIT)

  • • Programmable Interval Timer
  • • 3 × 16-bit counters
  • • 6 operating modes
  • • Used for timing, counting, PWM

8251 (USART)

  • • Universal Sync/Async Receiver/Transmitter
  • • Serial communication
  • • Programmable baud rate
  • • Full duplex operation

ADC/DAC Interfacing

ADC (Analog to Digital)

  • ADC0804: 8-bit, successive approximation
  • Resolution: n-bit = 2ⁿ levels
  • Step size = Vref / 2ⁿ
  • Applications: Sensors, audio

DAC (Digital to Analog)

  • DAC0808: 8-bit, current output
  • Output = (D × Vref) / 2ⁿ
  • May need op-amp for voltage output
  • Applications: Audio, motor control

Display Interfacing

7-Segment Display

  • • Common anode or common cathode
  • • Use decoder (7447) or direct drive
  • • Multiplexing for multiple digits

LCD (16×2)

  • • HD44780 controller
  • • 4-bit or 8-bit mode
  • • RS, RW, E control signals

8. Key Takeaways for CpE Students

Essential Formulas & Concepts

8086 Memory

  • • Physical = Segment × 16 + Offset
  • • 20-bit address = 1 MB
  • • Each segment = 64 KB max

8051 Timer

  • • Machine cycle = 12 / Fosc
  • • Mode 1: 65536 - count
  • • Mode 2: 256 - count (auto-reload)

ADC/DAC

  • • Resolution = Vref / 2ⁿ
  • • 8-bit: 256 levels
  • • 10-bit: 1024 levels

Baud Rate

  • • 8051: TH1 = 256 - (Fosc / (384 × Baud))
  • • Common: 9600, 19200, 115200

Common Interrupt Vectors (8051)

Reset: 0000h

INT0: 0003h

Timer0: 000Bh

INT1: 0013h

Timer1: 001Bh

Serial: 0023h

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